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? freescale semiconductor, in c., 2013. all rights reserved. freescale semiconductor user?s guide document number: KTPF0100UG rev. 2.0, 2/2013 kitpf0100epevbe evaluation board featuring the mmpf0100 1 4-channel configurable pmic figure 1. kitpf0100epevbe evaluation board contents 1 kit contents / packing list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 2 important notice . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 3 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 4 kitpf0100epevbe features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 5 hardware/software requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 6 software and drivers installation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 7 hardware configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 8 evaluation board schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 9 hardware description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 10 graphical user interface description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 11 kitpf0100epevbe board layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 12 bill of materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 13 references . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 14 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
KTPF0100UG , rev. 2.0 2 freescale semiconductor kit contents / packing list 1 kit contents / packing list ? customer evaluation board kitpf0100epevbe ? kitpf0100epevbe quick start guide ? warranty card and technical support brochure
KTPF0100UG , rev. 2.0 freescale semiconductor 3 important notice 2 important notice freescale provides the enclosed product(s) under the following conditions: this evaluation kit is inte nded for use of engineering development or evaluation purposes only. it is provided as a sample ic pre-sold ered to a printed circuit board to make it easier to access inputs, outputs, and supply terminals. th is evb may be used with any development system or other source of i/o signals by simply connecting it to the host mcu or computer board via off-the-shelf cables. this evb is not a refere nce design and is not intended to represent a final design recommendation for any particular ap plication. final device in an ap plication will be he avily dependent on proper printed circuit board layout and heat sinking design as well as attention to supply filtering, transient suppression, and i/o signal quality. the goods provided may not be complete in terms of required design, marketing, and or manufacturing related protective considerations, including product safety measures typically found in the end product incorporating the goods. due to the ope n construction of the product, it is the user's responsibility to take any and all appropriate precautions with regard to el ectrostatic discharge. in order to minimize risks associated with the customers applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. for any safety concerns, contact freescale sales and technical support services. should this evaluation kit not meet the specifications indicated in the kit, it may be returned within 30 days from the date of delivery and will be replaced by a new kit. freescale reserves the right to make changes withou t further notice to any products herein. freescale makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does freescale assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation c onsequential or incidental damages. ?typical? parameters can and do vary in different applications and actual performance may vary over time. all operating parame ters, including ?typical?, must be validated for each customer application by customer?s technical experts. freescale does not convey any license under its patent rights nor the ri ghts of others. freescale products are not designed, intended, or authorized for use as co mponents in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the freescale product could create a si tuation where personal injury or death may occur. should buyer purchase or use freescale products for any such unintended or unauthorized application, buyer shall indemnify and hold freescale and its of ficers, employees, subsid iaries, affiliates, and distributors harmless against all claims, costs, dama ges, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of pers onal injury or death associated with such unintended or unauthorized use, even if such claim alleges that freescale was negligent regarding the design or manufacture of the part.freescale? and the freescal e logo are trademarks of freescale semiconductor, inc. all other product or service names ar e the property of their respective owners. ? freescale semiconductor, inc. 2013
KTPF0100UG , rev. 2.0 4 freescale semiconductor introduction 3 introduction the kitpf0100epevbe evaluation board a llows full evaluation capability of the pf0100 pmic for the i.mx6 family of application processors. it provides access to all output voltage rails as well as control and signal pins through terminal block connectors for an easier out-of -the-box evaluation experience. a single terminal block connector for the input power supply allows the user to su pply the board with an external dc power supply to fully evaluate the performance of the device. the kitpf0100epevbe comes with a non-programme d version of the pf0100 pmic, so it is prep ared to power up from the default sequence. however, an integrated control/fuse programming interface is provided to allow the customer to program the otp/tbb (one time programmable/try-before-buy) memory and also to select it as the default source for the power-up conf iguration. likewise, the programming interface allows full control of the pf0100 through the i 2 c communication lines. this document is inte nded to provide an overview of the kitpf0100epevbe evaluati on board as well as detailed instruction for programming the pf0100 through its dedicated graphic user interface (gui). note: this document provides updated inform ation on the installation and use of the current pf 0100 evk control gui, revision 3.0.0.20. some discrepancies may be found if using an earlier version of the gui. to learn about the version of the gui you are using, please refer to section ? graphical user interface description ?. 4 kitpf0100epevbe features ? input voltage operation range from 3.1 v to 4.5 v ? output voltage supplies accessible through detachable terminal blocks ? four to six independent buck converters ? one 5.0 v boost regulator ? six general purpose ldo regulators ? one ddr memory termination voltage reference ? one vsrtc supply ? coin cell support for ?try-before-buy? (tbb) mode ? on/off push button support ? hardware configuration flexibility throu gh various jumper he aders and resistors ? integrated usb to i 2 c programming interface for full control/configuration ? onboard otp programming supply and control ? onboard pmic control through the i 2 c register map ? fully featured programmer through j36 for external device control/programming ? on board connectors for interfacing with future evaluation/debug tools ? compact form factor (4 x 4 in 2 )
KTPF0100UG , rev. 2.0 freescale semiconductor 5 hardware/software requirements 5 hardware/software requirements 5.1 hardware requirements ? power supply: ? output voltage range from 3.1 v to 4.5 v ? current capability from 3 to 5 a (current requirement is dependent on output loading) ? supply to board connection cables (capable of withstanding up to 5 a current) ? usb (male) to mini usb (male) communication cable. ? usb-enabled computer. 5.2 software requirements ? windows xp or windows 7 operating system ? microsoft .net framework 4.0 ? ni-visa 5.1.2 communication package + developm ent support with .net framework 4.0 languages support ? kitpf0100gui.zip: graph ical user interface (gui) for kitpf0100epevbe
KTPF0100UG , rev. 2.0 6 freescale semiconductor software and drivers installation 6 software and drivers installation 1. install microsoft .net framework 4.0, download and run "dotnetfx40_ client_x86_x84.exe ". click on link below http://www.microsoft.com/en-us/download/details.aspx?id=24872 2. install windows installer 3.1 (windows xp only), download and run "windowsinstaller-kb93803-v2-x 86.exe ".onl click on link below http://www.microsoft.com/en-us /download/details.aspx?id=25 3. install ni-visa 5.1.2, download and run "visa512.exe". click on link below ni-visa 5.1.2 - national instruments note: it is the customer?s re sponsibility to obtain any license files from national instruments th at are necessary for enabling the ni-visa 5.1.2 drivers. when installing the ni-visa 5.1.2, ma ke sure to select the .net framework 4.0 langua ge support drivers as shown in figure 2 . figure 2. ni-visa 5.1.2 features install window
KTPF0100UG , rev. 2.0 freescale semiconductor 7 software and drivers installation 6.1 using ni visa driver wi zard to install .inf file 1. go to start > programs > national instruments > visa > driver wizard 2. select usb under hardware bus selection and press ?next? button ?
KTPF0100UG , rev. 2.0 8 freescale semiconductor software and drivers installation 3. enter "15a2" in the vendor id and "00f5" in th e product id fields and press the ?next? button. figure 4. ni-visa usb device information window
KTPF0100UG , rev. 2.0 freescale semiconductor 9 software and drivers installation 4. enter "pf0100-evaluation" in the instrument prefix fi eld, browse to a folder where you want to save the output file and press the ?next? button c:\my documents\national instruments\ni-visa\ pf0100-evaluation c:\my documents\national instruments\ni-visa\pf0100-evaluation\ pf0100-evaluation.inf figure 5. ni-visa output file generation window
KTPF0100UG , rev. 2.0 10 freescale semiconductor software and drivers installation 5. select the option of automatically installing the generated .inf driver and press the ?finish? button. ?
KTPF0100UG , rev. 2.0 freescale semiconductor 11 software and drivers installation 7. to check if the usb device driver was installed correctly, go to start > setting > control panels> system > device driver. you should see "pf0100-eval uation board" under "ni-visa usb devices". ?
KTPF0100UG , rev. 2.0 12 freescale semiconductor software and drivers installation 6.2 installing the kitpf0100gui 1. create a directory on your pc as follows:
KTPF0100UG , rev. 2.0 freescale semiconductor 13 hardware configuration 7 hardware configuration by default, the kitpf0100epevbe evalua tion board is set to power up from the defa ult power-up sequence. verify that the jumpers are placed in the right position as shown in figure 9 . for a detailed description of the jumper functionality, refer to table 1 . igure .defaultumperconfigurationdiagram
KTPF0100UG , rev. 2.0 14 freescale semiconductor hardware configuration connect the power supply and the usb communication cables as shown in figure 10 . voltmeters are optional but it are recommended in order to accurately verify that each on e of the output supplies is providing the correct voltage level. figure 10. evaluation board setup note: the kitpf0100epevbe allows the sele ction of sw2 regulator output or an external 3.3v ldo output as the vddio/i 2 c pull-up supply. by default, the sw2 regulator is the source for the vddio supply (j30 = 3-2). if the sw2 regulator is to be set below 3.0v then make sure the 3.3v ldo output is c onnected to vddio and the i 2 c pull-up resistors by removing r34 and r 33 and shorting pins 1, 2 and 3 of j30.
gnd pvin input supplies ldo inputs sense vgen sense vdd otp closed closed 2-3 closed closed 6.8mm place bottom 6.8mm leaded place top closed swvin vgen1 vgen2 vgen3 vgen4 vgen5 vin3 vgen1 vgen2 vgen3 vgen4 vgen5 vgen6 vsnvs vin2 vin1 vcoredig vcoreref vcore vddotp ictest vsnvs vddotp vcoredig vddotpin vgen6 standby vin2 vin1 vrefddr vddio vgen1 vgen2 vgen3 vgen4 vgen5 vgen6 vin vin vin pvin vsnvs vsnvs pvin pvin pvin swvin swvin mcu_sda sw3a sw3b mcu_scl pwron standby sw4 3v3 intb resetbmcu sdwnb vgen1 vgen2 vgen3 vgen4 vgen5 vgen6 vsnvs 3v3 sw2 sw2 sw2 sw2 sw4 sw4 vddotpin vsnvs c44 0.1uf vgen3 dnp c51 1.0uf vgen1 dnp mmpf0100npep u1b vgen1 16 vgen2 18 vin3 40 vhalf 29 vin1 17 vgen6 41 vinrefddr 30 vrefddr 31 vsnvs 43 vgen3 26 vgen4 28 vin2 27 licell 42 vgen5 39 r20 0 dnp vddotp1 dnp r24 0 dnp c39 10.0uf vgen4 dnp c40 1.0uf c43 2.2uf j40 hdr 1x2 th 1 2 vddio1 dnp j22 hdr 1x3 1 2 3 r27 0 dnp r23 0 dnp vgen6 dnp + - bat2 bk-879 1 3 2 consumer/industrial mmpf0100npep u1a ictest 5 intb 1 resetbmcu 3 scl 54 sda 53 sdwnb 2 standby 4 vcoredig 51 vcoreref 52 vddio 55 vddotp 47 pwron 56 vcore 49 gndref 48 vin 50 r47 0 sw1 fsmsm 1 2 c41 4.7uf vin_sense1 dnp pwron1 dnp c50 1.0uf r31 10.0k vrefddr1 dnp j26 hdr 1x2 th 1 2 c45 0.1uf vin2 dnp vin3 dnp j30 hdr 1x3 1 2 3 c54 1.0uf c47 0.47uf r35 0 c42 2.2uf sda1 dnp r32 10.0k vcore1 dnp r29 100k c52 1.0uf standby1 dnp r37 4.7k r33 0 dnp vgen5 dnp c56 0.1uf j25 subassy_tb_3x1 1 2 3 c87 1.0uf j24 hdr 1x2 th 1 2 sdwnb1 dnp r22 0 vin1 dnp c55 1.0uf dnp c48 1.0uf c53 0.22uf bat1 licell 1 2 c35 4.7uf c46 0.22uf vhalf1 dnp intb1 dnp c38 2.2uf r26 0 r25 0 r46 0 r28 1m c37 10.0uf scl1 dnp vcoreref1 dnp c34 2.2uf j27 hdr 1x2 th 1 2 vsnvs1 dnp c36 10.0uf c84 1.0uf r43 0 j20 hdr 1x3 1 2 3 c49 1.0uf r36 4.7k resetbmcu1 dnp vcoredig1 dnp r30 10.0k r34 0 ictest1 dnp j17 hdr 2x3 1 2 3 4 6 5 vgen2 dnp r21 0 vinrefddr1 dnp r79 100k j41 hdr 1x2 th 1 2 KTPF0100UG , rev. 2.0 freescale semiconductor 15 evaluation board schematic 8 evaluation board schematic figure 11. kitpf0100epevbe ldo/con t rol schematic part 1
reset indicator reserved indicator interrupt indicator mounting holes gnd's i2c terminal blocks interface terminal blocks ldo terminal blocks hot plug workaround gnd vgen1 vgen2 vgen3 vgen4 vgen5 vgen6 vsnvs gnd intb sdwnb resetbmcu standby pwron gnd gnd gnd vrefddr gnd vddio gnd vcoredig pvin pvin pvin pvin pvin swvin pvin resetbmcu mcu_sda intb mcu_scl vgen1 vgen2 vgen3 vgen4 vgen5 vgen6 vsnvs vrefddr standby pwron intb sdwnb resetbmcu swbst vddio mcu_scl mcu_sda sw1c sw1c sw1ab sw1ab sw4 sw4 sw2 sw2 sw3b sw3b sw3a sw3a d2 led red a c j16 subassy_tb_3x1 1 2 3 bh4 mtg r80 27k r84 0 dnp j19 subassy_tb_3x1 1 2 3 r38 200 ohm 1 2 gnd3 dnp r39 200 ohm 1 2 q3 fdv302p 1 3 2 c85 2.2uf dnp bh2 mtg d3 led red a c j21 subassy_tb_3x1 1 2 3 j42 hdr_2x10 dnp 1 2 3 4 6 5 7 8 9 10 11 12 13 14 15 16 17 18 19 20 r40 200 ohm 1 2 u7 mic5205 in 1 gnd 2 adj 4 en 3 out 5 r83 0 dnp j18 subassy_tb_3x1 1 2 3 j32 subassy_tb_3x1 1 2 3 gnd5 dnp r81 470k j44 hdr_2x10 dnp 1 2 3 4 6 5 7 8 9 10 11 12 13 14 15 16 17 18 19 20 j33 sub_tb_2x1 1 2 bh3 mtg red grn d4 led_red-grn 4 2 1 3 bh1 mtg q2 fdv302p 1 3 2 gnd1 dnp gnd6 dnp gnd2 dnp j31 sub_tb_2x1 1 2 gnd4 dnp j43 hdr_2x10 dnp 1 2 3 4 6 5 7 8 9 10 11 12 13 14 15 16 17 18 19 20 c86 470pf r69 200 ohm 1 2 g d s g s d q1 fdc6327c 2 6 1 5 4 3 j29 subassy_tb_3x1 1 2 3 r82 0 dnp KTPF0100UG , rev. 2.0 16 freescale semiconductor evaluation board schematic figure 12. kitpf0100epevbe ldo/c ontrol schematic part 2
closed closed closed closed closed closed closed closed sw3afb sw1abfb sw1bin sw3bin sw3blx sw3alx sw1clx sw2lx swbstin sw1cfb sw1cfb sw1vsssns sw2lx sw2fb sw3afb sw2fb sw4lx sw4lx sw4fb sw1blx sw4fb sw1alx sw3bfb sw4in swbstfb swbstfb sw1abfb sw1cin swbstlx sw1clx sw1blx sw1alx sw3blx sw3bfb sw3alx swvin swvin swvin swvin swvin swvin swvin swvin sw2 sw4 sw1ab sw3a sw3b swbst sw1c c33 22uf r17 0.001 dnp lx_swb1 dnp l1 2.2uh 1 2 l7 1uh 1 2 j9 hdr 1x2 th 1 2 j8 sub_tb_2x1 1 2 l8 1uh 1 2 sw4 dnp c7 0.1uf j3 hdr 1x2 th 1 2 c15 0.01uf c18 10uf c31 22uf c20 2.2uf j5 hdr 1x2 th 1 2 c83 22uf lx_swa1 dnp r2 1.0 dnp l4 1uh 1 2 r1 0.001 vin_swa1 dnp vin_swc1 c10 0.1uf c29 22uf c13 4.7uf r7 0.001 dnp vin_sw2 c14 0.1uf j2 hdr 1x2 th 1 2 c16 22uf r70 0.001 dnp c32 22uf c5 4.7uf swb3 dnp j12 sub_tb_2x1 1 2 c12 4.7uf c21 22uf c30 22uf swa3 dnp vin_swb1 c2 0.1uf vin_swbst1 dnp vswbst1 dnp c28 22uf d1 mbr120lsft1g a c c25 22uf r4 0.001 l5 1uh 1 2 c23 22uf dnp c11 0.1uf l3 1uh 1 2 c9 4.7uf lx_swbst1 dnp r16 0.001 r85 0 j6 hdr 1x2 th 1 2 c26 22uf j11 sub_tb_2x1 1 2 r3 0.001 c1 4.7uf c8 4.7uf lx_swa3 dnp lx_sw2 dnp r6 0.001 j10 sub_tb_2x1 1 2 vin_swa3 dnp lx_sw4 dnp c24 22uf dnp r9 0.001 dnp lx_swb3 dnp vin_swb3 dnp j13 sub_tb_2x1 1 2 j4 hdr 1x2 th 1 2 sw2 dnp r11 0.001 vin_sw4 dnp j14 sub_tb_2x1 1 2 j15 sub_tb_2x1 1 2 r10 0.001 dnp r8 0.001 c19 0.1uf c27 22uf j1 hdr 1x2 th 1 2 j7 hdr 1x2 th 1 2 swc1 dnp c17 1000pf dnp c22 22uf c4 0.1uf c6 0.1uf lx_swc1 dnp swab1 dnp l2 1uh 1 2 l6 1uh 1 2 c3 4.7uf c82 22uf mmpf0100npep u1c sw1cin 12 sw1vsssns 14 sw2in_1 23 sw3afb 38 sw3ain 37 sw3alx 36 sw3bfb 33 sw3bin 34 sw3blx 35 sw3vsssns 32 sw4fb 19 sw4in 20 swbstfb 44 swbstin 45 swbstlx 46 sw1ain 7 sw1alx 8 sw1bin 10 sw1blx 9 sw1cfb 13 sw1clx 11 sw1fb 6 sw2fb 25 sw2lx 22 sw4lx 21 epgnd 57 gndref1 15 sw2in_2 24 KTPF0100UG , rev. 2.0 freescale semiconductor 17 evaluation board schematic figure 13. kitpf0100epevbe switch ing regulator s schematic
programming interface usb connector type a bdm programmer esd protection crystal main ic mc9s08jm60 led indicators 8v - boost converter closed ldo regulator 3.3v vout = 1.242 x ( (r2/r1) + 1) = 3.3v r2 = ((vout/1.242) -1) x r1 r1 r2 place on bottom place on bottom place on bottom place on bottom place on bottom d- d+ g vv usbdn usbdp usbpwr rstm6 mcuscl mcusda id1 id extalm6 xtalm6 extalm6 xtalm6 bkgdm6 bsten vusben 3v3en vpgmen lron lgon id id1 usbdn usbdp vusb33 vusb33 rstm6 bkgdm6 lgon lron pwron mcuscl bsten bstdn bstup vpgmen bstup bstdn vddotpin 3v3 3v3en vinusb gpio1 gpio2 mcusda vusben vinusb vddotpinsns vddotpinsns usbpwr usbpwr usbpwr usbpwr usbpwr pvin vddotpin 3v3 pwron gpio2 mcusda mcuscl gpio1 vinusb 3v3 vinusb r3 u4 max686 lx 16 vcc 12 iset 6 vdd shdn dn 3 up 2 pok 11 lcdon 14 re pgnd 1 b 1 nc 1 dacout 8 pol 4 gnd 13 r1 4.k l hi1812v11r-1 1 2 1 dn36p 1 3 2 c6 22p 1 2 r1 2k r6 4 1 2 3 hdr2x3 1 2 3 4 6 c64 .4u c8 1.u c .1u r 1k r48 1.k dnp c62 .1u r66 4k + c1 1u d esdl.stg a c r41 1m 1 2 bss138 1 2 3 l1 22uh 1 2 r6 1k r6 4k c61 22p 1 2 u2 mcs8m6cgte ptc4 1 ir/tpmclk 2 reset 3 pt/tpm1ch2 4 pt1/tpm1ch3 pt4/tpm2ch 6 pt/tpm2ch1 pte/td1 pte1/rd1 1 pte2/tpm1ch 11 pte3/tpm1ch1 12 pte4/miso1 13 pte/mosi1 14 pte6/spsck1 1 pte/ss1 16 vdd 1 vss 18 usbdn 1 usbdp 2 vusb33 21 ptg/kbip 22 ptg1/kbip1 23 ptb/miso2/adp 26 ptb1/mosi2/adp1 2 ptb2/spsck2/adp2 28 ptb3/ss2/adp3 2 ptb4/kbip4/adp4 3 ptb/kbip/adp 31 ptd/adp8/acmp+ 32 ptd1/adp/acmp- 33 vddad/vreh 34 vssad/vrel 3 ptd2/kbip2/acmpo 36 ptg2/kbip6 38 ptg3/kbip 3 bkgd/ms 4 ptg4/xtal 41 ptg/extal 42 vssosc 43 ptc/scl 44 ptc1/sda 4 ptc2 46 ptc3/td2 4 ptc/rd2 48 pt6 8 pta 2 pta 24 ptd 3 gnd 4 r 4k vbusd-d+idg usb-minib 34 1 2 3 4 s2 s1 s3 s4 3 hdr1x3 1 2 3 1 12mh i/o1 1 gnd4 4 i/o3 3 gnd2 2 d11 ledred a c d mbr13lst1g a c c63 .1u r4 1.k dnp d6 esdl.stg a c c4 .1u u mic2 in 1 gnd 2 ad 4 en 3 out r6 4k r61 12k c 2.2u dnp r64 1k r4 d8 esdl.stg a c r2 12.k c6 .1u + c 1u 1 .a 1 2 r 1 + c3 4.u + c66 4.u 36 hdr2x4 1 2 3 4 6 8 r 34k c2 22p c8 4p r42 33 1 2 r63 1k r 4.k c6 .1u 8 bss138 1 2 3 6 dn36p 1 3 2 dn36p 1 3 2 c .1u d esdl.stg a c + c81 2.2u c8 .1u l11 hi1812v11r-1 1 2 r8 1k r68 4 1 2 r6 64k c 1u d1 ledgreen a c r4 33 1 2 programming connector KTPF0100UG , rev. 2.0 18 freescale semiconductor evaluation board schematic figure 14. kitpf0100epevbe control/progr am ming interface schematic
KTPF0100UG , rev. 2.0 freescale semiconductor 19 hardware description 9 hardware description the kitpf0100epevbe ope rates with a single power supply from 3.1 to 4.5 v and is controlled via usb with help of an integrated usb-i 2 c communication bridge. by applying the in put voltage supply, the kitpf0100epevbe will power up according to the default power-up sequence described in the pf0100 datasheet. furthermore, for controlling the pf0100 device or programming the otp r egisters, refer to section graphical user interface description for a d etailed description of the kitpf0100gui software. important notice: if p ower-up sequences and configuration are to be modified, the user must ensure that the register settings are consistent with the hardware configur ation. this is most important for the buck regulators, where the quantity, size, and value of the inductors depend on the configuration (single/dual phase or independent mode) and the switching freque ncy. additionally, if an ldo is powered by a buck regulato r, it will be gated by the buck regulator in the start-up sequence. refer to the mmpf0100 datasheet for details on buck regulator setup. 9.1 jumper description table 1. kitpf0100epevbe jumper description jumper default description j1 - j7 closed buck regulators input power path isolation.
KTPF0100UG , rev. 2.0 20 freescale semiconductor hardware description 9.2 connectors and terminal blocks description table 2. terminal blocks descriptions connector function pin definition j8 swbst pin 1 - swbst output pin 2 - gnd j10 sw1ab pin 1 - sw1ab output pin 2 - gnd j11 sw1c pin 1 - sw1c output pin 2 - gnd j12 sw2 pin 1 - sw2 output pin 2 - gnd j13 sw4 pin 1 - sw4 output pin 2 - gnd j14 sw3a pin 1 - sw3a output pin 2 - gnd j15 sw3b pin 1 - sw3b output pin 2 - gnd j16 vgen1/vgen2 pin 1 - vgen1 output pin 2 - gnd pin 3 - vgen2 output j18 vgen3/vgen4 pin 1 - vgen3 output pin 2 - gnd pin 3 - vgen4 output j19 vgen5/vgen6 pin 1 - vgen5 output pin 2 - gnd pin 3 - vgen6 output j21 vsnvs/vrefddr pin 1 - vsnvs output pin 2 - gnd pin 3 - vrefddr output j25 main input supply pin 1 - gnd pin 2 - pvin pin 3 - swvin j29 interfacing 1 pin 1 - intb pin 2 - sdwnb pin 3 - resetbmcu j32 interfacing 2 pin 1 - standby pin 2 - pwron pin 3 - gnd j31 i 2 c signals pin 1 - scl pin 2 - sda j33 vddio pin 1 - vddio pin 2 - gnd
KTPF0100UG , rev. 2.0 freescale semiconductor 21 hardware description figure 15. input/output terminal blocks
table 3. connector description connector function pin definition j34 mini usb connector pin 1 - vbus pin 2 - d- pin 3 - d+ pin 4 - nc pin 5 - gnd chassis - gnd j35 bdm connector pin 1 - bkgd_jm60 pin 2 - gnd pin 3 - nc pin 4 - rst_jm60 pin 5 - nc pin 6 - usb_pwr j36 programmer connector pin 1 - vddotpin (8.5v boost output) pin 2 - 3v3 (3.3 v ldo output) pin 3 - gnd pin 4 - mcu_scl (i 2 c clock signal) pin 5 - mcu_sda (i 2 c data signal) pin 6 - pwron (controls the pwron on the target device) pin 7 - gpio 1 (general purpose gpio) pin 8 - gpio 2 (general purpose gpio) j42 debug port 1 debugging connector for future development tools. sw1c sw1c sw1ab sw1ab sw4 sw4 sw2 sw2 sw3b sw3b sw3a sw3a j42 hdr_2x10 dnp 1 2 3 4 6 5 7 8 9 10 11 12 13 14 15 16 17 18 19 20 j43 debug port 2 debugging connector for future development tools vgen1 vgen2 vgen3 vgen4 vgen5 vgen6 vsnvs vrefddr st j43 hdr_2x10 dnp 1 2 3 4 6 5 7 8 9 10 11 12 13 14 15 16 17 18 19 20 j44 debug port 3 debugging connector for future development tools swvin pvin standby pwron intb sdwnb resetbmcu swbst vddio mcu_scl mcu_sda j44 hdr_2x10 dnp 1 2 3 4 6 5 7 8 9 10 11 12 13 14 15 16 17 18 19 20 KTPF0100UG , rev. 2.0 22 freescale semiconductor hardware description
KTPF0100UG , rev. 2.0 freescale semiconductor 23 hardware description 9.3 debug and configuration components the kitpf0100epevbe allows full flexib ility to change the default config uration of sw1a/b/c and sw3a/b outputs to one more suitable for a specific application scen ario. it also provides several source options for the ldo supplies to test various load ing and supplying scenarios. test point are provided on key nodes of the kitpf0100epevbe to a llow full debugging capability during application development. 9.3.1 sw1a/b/c config uration components sw1abfb sw1cfb sw1blx sw1alx sw1clx sw1ab sw1c lx_swb1 dnp lx_swa1 dnp l4 1uh 1 2 r7 0.001 dnp c21 22uf l3 1uh 1 2 c23 22uf dnp r4 0.001 c25 22uf j11 sub_tb_2x1 1 2 c26 22uf j10 sub_tb_2x1 1 2 r6 0.001 r11 0.001 r9 0.001 dnp c24 22uf dnp r8 0.001 r10 0.001 dnp c22 22uf swc1 dnp l2 1uh 1 2 swab1 dnp lx_swc1 dnp figure 16. sw1a/b/c output configuration the sw1a/b/c regulator can be configured in va rious operating modes as described in table 4 . table 4. sw1abc configuration chart component sw1a/b/c single phase sw1a/b single phase sw1c independent sw1a/b dual phase sw1c independent r6 closed closed dnp r9 closed dnp dnp r4 closed closed closed r7 closed dnp closed r8 dnp dnp closed r10 closed dnp dnp r11 dnp closed closed l2 1.0
KTPF0100UG , rev. 2.0 24 freescale semiconductor hardware description 9.3.2 sw3a/b configuration components sw3afb sw3blx sw3alx sw3bfb sw3a sw3b r17 0.001 dnp c33 22uf l7 1uh 1 2 l8 1uh 1 2 c31 22uf swb3 dnp c32 22uf r70 0.001 dnp swa3 dnp c30 22uf r16 0.001 lx_swa3 dnp lx_swb3 dnp j15 sub_tb_2x1 1 2 j14 sub_tb_2x1 1 2 figure 17. sw3a/b output configuration the sw3a/b regulator can be configured in var ious operating modes as described in table 5 . table 5. sw3abc configuration chart component sw3a/b single phase sw3a/b dual phase sw3a independent sw3b independent r16 closed dnp dnp r17 closed closed dnp r70 dnp closed closed l7 1.0 closed 6.8mm place bottom 6.8mm leade place top vgen1 vgen2 vgen3 vgen4 vgen5 vin1 vin3 vrefddr vsnvs vin2 vgen6 vgen1 vgen2 vgen3 vgen4 vgen5 vgen6 vin vsnvs sw3a sw3b sw4 sw2 sw2 sw2 sw4 c44 0.1uf c43 2.2uf c40 1.0uf r24 0 dnp r20 0 dnp mmpf0100npep u1b vgen1 16 vgen2 18 vin3 40 vhalf 29 vin1 17 vgen6 41 vinrefddr 30 vrefddr 31 vsnvs 43 vgen3 26 vgen4 28 vin2 27 licell 42 vgen5 39 r23 0 dnp r27 0 dnp + - bat2 bk-879 1 3 2 vrefddr1 dnp c41 4.7uf c45 0.1uf c47 0.47uf c42 2.2uf r22 0 c35 4.7uf bat1 licell 1 2 r25 0 r26 0 c38 2.2uf vhalf1 dnp c46 0.22uf c34 2.2uf c84 1.0uf j20 hdr 1x3 1 2 3 vinrefddr1 dnp r21 0 figure 18. ldo schematic configuration
2-3 closed closed vcoredig vcoreref vcore vddotp ictest vddio intb sdwnb resetbmcu standby pwron vin pvin vsnvs pvin mcu_sda mcu_scl pwron standby 3v3 intb resetbmcu sdwnb 3v3 sw2 sw4 vddotp1 dnp c51 1.0uf j22 hdr 1x3 1 2 3 vddio1 dnp sw1 fsmsm 1 2 r47 0 consumer/industrial mmpf0100npep u1a ictest 5 intb 1 resetbmcu 3 scl 54 sda 53 sdwnb 2 standby 4 vcoredig 51 vcoreref 52 vddio 55 vddotp 47 pwron 56 vcore 49 gndref 48 vin 50 j26 hdr 1x2 th 1 2 r31 10.0k pwron1 dnp vin_sense1 dnp c54 1.0uf j30 hdr 1x3 1 2 3 r37 4.7k standby1 dnp c52 1.0uf vcore1 dnp sda1 dnp r35 0 c56 0.1uf j32 1 2 r33 0 dnp c55 1.0uf dnp sdwnb1 dnp c53 0.22uf vcoreref1 dnp scl1 dnp r28 1m r46 0 vcoredig1 dnp resetbmcu1 dnp r36 4.7k r43 0 j29 subassy_tb_3x1 1 2 3 ictest1 dnp r34 0 r30 10.0k KTPF0100UG , rev. 2.0 freescale semiconductor 25 hardware description figure 19. logic and core supplies schematic table 6. ldo input supply configuration chart input pin input options vin1 input supply for vgen1 and vgen2 r20 = sw4 r21 = sw2 vin2 input supply for vgen3 and vgen4 r24 = sw4 r22 = sw2 vin3 input supply for vgen5 and vgen6 r23 = vin r25 = sw2 vinrefddr vrefddr input supply r26 = sw3a r27 = sw3b vddio vddio input supply r33 = sw4 r34 = sw2 1. make sure to populate only one option per input pin to avoid shorts between various sources.
KTPF0100UG , rev. 2.0 26 freescale semiconductor hardware description 9.3.4 test point all test points are clearly marked on the kitpf0100epevbe ev aluation board. figure 20 shows the location of various test points of interest during evaluation. figure 20. key test point locations and default voltages
KTPF0100UG , rev. 2.0 freescale semiconductor 27 hardware description 9.4 miscellaneous components 9.4.1 power on push button a footprint for a normally open, momentary push-button is provided at the pwron terminal to allow a momentary low state by pressing the push button . r43 allows isolation of the pwron terminal from the mcu gpio controlling this pin. vsnvs pwron standby intb resetbmcu sdwnb sw1 fsmsm 1 2 u1a intb 1 resetbmcu 3 sdwnb 2 standby 4 vcoredig 51 vcoreref 52 vddio 55 vddotp 47 pwron 56 vcore 49 gndref 48 vin 50 j26 hdr 1x2 th 1 2 pwron1 dnp r28 1m r43 0 figure 21. power on circuit 9.4.2 pmic led indicators led indicators are provided to notify the pmic status to the user. figure 22 shows the pmic status leds d2 and d4, and a reserved led indicator d3, that allows for an ex ternal rework connection to the transistor gate if any given signal debug is required. reset indicator shutdown indicator interrupt indicator pvin pvin pvin pvin resetbmcu intb d2 led red a c r38 200 ohm 1 2 r84 0 dnp r39 200 ohm 1 2 q3 fdv302p 1 3 2 d3 led red a c r40 200 ohm 1 2 q2 fdv302p 1 3 2 red grn d4 led_red-grn 4 2 1 3 r69 200 ohm 1 2 g d s g s d q1 fdc6327c 2 6 1 5 4 3 reserved figure 22. pmic status indicator
KTPF0100UG , rev. 2.0 28 freescale semiconductor hardware description table 7 describes the meaning of the led states. table 7. led state description led description d2 interrupt no tification on = pmic has detected an unmasked interrupt off = no interrupt detected d4 resetbmcu notification green = pmic is in regulation and operating properly red = pmic is out of regulation d3 reserved debug led on = q3 gate (r84 pad) is low off = q3 gate (r84 pad) is high or floating
KTPF0100UG , rev. 2.0 freescale semiconductor 29 hardware description 9.4.3 control/programming interface this onboard usb-to-i 2 c interface comprises three basic blocks. 1. controlling mcu (mc9s0 8j m60cgte) for usb-i 2 c translation. 2. 3.3v ldo supply for external device controlling. 3. 8.25v boost converter for otp programming. the control/programming interface allows one to program th e onboard pf0100 pmic. alternatively, the interface can serve as a programmer for external devices though the connector j36. programming interface usb connector type a bdm programmer esd protection crystal main ic mc9s08jm60 led indicators 8v - boost converter closed ldo regulator 3.3v vout = 1.242 x ( (r2/r1) + 1) = 3.3v r2 = ((vout/1.242) -1) x r1 r1 r2 place on bottom place on bottom place on bottom place on bottom place on bottom d- d+ g vv usbdn usbdp usbpwr rstm6 mcuscl mcusda id1 id extalm6 xtalm6 extalm6 xtalm6 bkgdm6 bsten vusben 3v3en vpgmen lron lgon id id1 usbdn usbdp vusb33 vusb33 rstm6 bkgdm6 lgon lron pwron mcuscl bsten bstdn bstup vpgmen bstup bstdn vddotpin 3v3 3v3en vinusb gpio1 gpio2 mcusda vusben vinusb vddotpinsns vddotpinsns usbpwr usbpwr usbpwr usbpwr usbpwr pvin vddotpin 3v3 pwron gpio2 mcusda mcuscl gpio1 vinusb 3v3 vinusb r3 u4 max686 lx 16 vcc 12 iset 6 vdd shdn dn 3 up 2 pok 11 lcdon 14 re pgnd 1 b 1 nc 1 dacout 8 pol 4 gnd 13 r1 4.k l hi1812v11r-1 1 2 1 dn36p 1 3 2 c6 22p 1 2 r1 2k r6 4 1 2 3 hdr2x3 1 2 3 4 6 c64 .4u c8 1.u c .1u r 1k r48 1.k dnp c62 .1u r66 4k + c1 1u d esdl.stg a c r41 1m 1 2 bss138 1 2 3 l1 22uh 1 2 r6 1k r6 4k c61 22p 1 2 u2 mcs8m6cgte ptc4 1 ir/tpmclk 2 reset 3 pt/tpm1ch2 4 pt1/tpm1ch3 pt4/tpm2ch 6 pt/tpm2ch1 pte/td1 pte1/rd1 1 pte2/tpm1ch 11 pte3/tpm1ch1 12 pte4/miso1 13 pte/mosi1 14 pte6/spsck1 1 pte/ss1 16 vdd 1 vss 18 usbdn 1 usbdp 2 vusb33 21 ptg/kbip 22 ptg1/kbip1 23 ptb/miso2/adp 26 ptb1/mosi2/adp1 2 ptb2/spsck2/adp2 28 ptb3/ss2/adp3 2 ptb4/kbip4/adp4 3 ptb/kbip/adp 31 ptd/adp8/acmp+ 32 ptd1/adp/acmp- 33 vddad/vreh 34 vssad/vrel 3 ptd2/kbip2/acmpo 36 ptg2/kbip6 38 ptg3/kbip 3 bkgd/ms 4 ptg4/xtal 41 ptg/extal 42 vssosc 43 ptc/scl 44 ptc1/sda 4 ptc2 46 ptc3/td2 4 ptc/rd2 48 pt6 8 pta 2 pta 24 ptd 3 gnd 4 r 4k vbusd-d+idg usb-minib 34 1 2 3 4 s2 s1 s3 s4 3 hdr1x3 1 2 3 1 12mh i/o1 1 gnd4 4 i/o3 3 gnd2 2 d11 ledred a c d mbr13lst1g a c c63 .1u r4 1.k dnp d6 esdl.stg a c c4 .1u u mic2 in 1 gnd 2 ad 4 en 3 out r6 4k r61 12k c 2.2u dnp r64 1k r4 d8 esdl.stg a c r2 12.k c6 .1u + c 1u 1 .a 1 2 r 1 + c3 4.u + c66 4.u 36 hdr2x4 1 2 3 4 6 8 r 34k c2 22p c8 4p r42 33 1 2 r63 1k r 4.k c6 .1u 8 bss138 1 2 3 6 dn36p 1 3 2 dn36p 1 3 2 c .1u d esdl.stg a c + c81 2.2u c8 .1u l11 hi1812v11r-1 1 2 r8 1k r68 4 1 2 r6 64k c 1u d1 ledgreen a c r4 33 1 2 programming connector figure 23. control/programming int erface schematic
KTPF0100UG , rev. 2.0 30 freescale semiconductor graphical user interface description 10 graphical user interface description the kitpf0100 gui is based on a tabbed interface. each tabs can be selected to display a window associated with one functional aspect of the pf0100 device. 10.1 getting started 1. supply 3.6v to j25 of the evk boar d, then connect the usb cable from the usb-minib po rt (j34) to the computer. j30 should be in position (2-3); otherwise, you will receive an error message. 2. press the ?open session? button to se ar ch for the pf programmer device. 3. the ?select resource? dialog box should pop up, and you shou ld see the kitpf0100e pevbe device listed. the usb vendor id is 0x15a2, and the pa rt id is 0x00f5 fo r the kitpf0100epevbe. select the device and press the ?ok? button. ?
? ?
KTPF0100UG , rev. 2.0 32 freescale semiconductor graphical user interface description 10.2 verify i 2 c communication to pf0100 use the ?byte write? button to write one byte of data to register 0x1c of pf0100 and use the ?byte read? button to read back register content at address 0x1c to verify co rrect data was written. the log list should also reflect what i 2 c transactions the gui has processed. ? ?
KTPF0100UG , rev. 2.0 freescale semiconductor 33 graphical user interface description 10.3 gui features there are five functional tabs in the kitpf0100gui to a llow programming the pf0100 registers. they also permit one to perform either prototyping or one-time programming (otp) of the fuse registers. the power tab provides user access to control both the swit ching as well as the linear regulators on pf0100. the switching regulators can be programmed by sub-tabs for sw1, sw2, sw3, sw4, and swbst. for each of these tabs, the user has access to functional registers th at configure the output voltage, the standby voltage, the off-mode voltage, the phase control, the switching frequency and more. the user can also configure the otp register via the bottom half of the tab, which selects the start-up sequence of the switching regulators as well as phase configuration for sw1 and sw3. figure 29. switching regulators tab
KTPF0100UG , rev. 2.0 34 freescale semiconductor graphical user interface description linear regulators can be programmed using the linear sub-ta b. it enables the user to control the output voltage and the start-up sequence of the regulators as well as to choose between the standby and low power mode. figure 30. ldo regulators tab the interrupt s tab provides user access to the four interrupt regi sters in pf0100 functional register map. the user can choose to read the interrupts by pressing on the ?read interrupt x? button. each interrupt is latched so that even if the interrupt source be comes inactive, the interr upt will remain set until cleared. each interrupt can be cleared by writing a "1" to th e appropriate bit in the interrupt status register; this will also cause the intb pin to go high. each interrupt can be masked by setting the corresponding mask bit to a 1. as a result, when a masked interrupt bit goes high, the intb pin will not go low. a masked inte rrupt can still be read from th e interrupt status register. the sense registers contain status and inpu t sense bits so the system processor can poll the current state of interrupt sources. they are read only, and neither latched nor clearable.
KTPF0100UG , rev. 2.0 freescale semiconductor 35 graphical user interface description the user may choose to press the ?po ll interrupt x? cont rol to read the interrupts tab every 500ms. script editor figure 31. interrupts tab
KTPF0100UG , rev. 2.0 36 freescale semiconductor graphical user interface description the register bits tab allows bit programming of the pf0100 re gisters. this is an alternative to the i 2 c single byte write and read controls shown in section ? verify i2c communication to pf0100 ? . script editor figure 32. register bits tab
KTPF0100UG , rev. 2.0 freescale semiconductor 37 graphical user interface description the miscellaneous tab allows the user to read the silicon device id, configure the coin cell charger, enable ldo short-circuit protection, set the de-bounce time of logic io, and communicate with memory registers a-d. figure 33. miscellaneous tab
KTPF0100UG , rev. 2.0 38 freescale semiconductor graphical user interface description the evk test points tab provides a visual aid to the top layer of kitpf0100epevbe. figure 34. evk test point tab the script editor t ab allows one to create, load and save config uration scripts for the pf0100 device. for more information on how to create a configuration script, see section ? using the script editor ?.
KTPF0100UG , rev. 2.0 freescale semiconductor 39 graphical user interface description 10.4 using the script editor the script editor is a powerful tool that automates the pf0100 development process. scripts are groups of commands that are executed sequentially. they can quickly load pf0100 registers with your desired configuration, or they can help you to determine the correct power-up sequence for your design. scripts are stored as simple text files, and as such, can be edited with any text editor. since scripts are driven by your pc, pmic configurations can be explored and validated prior to connecting to a host i.mx processor. the script editor work area is shown in figure 35 . script files are created in the large work area to the left. the blank area to the right-hand side is the script log, whic h displa ys the script output as it steps sequentially. script area log area figure 35. script editor window
KTPF0100UG , rev. 2.0 40 freescale semiconductor graphical user interface description the following list describes all the availabl e buttons on the script editor tab. ? load script: launches the ?file load? dialog box allowing the user to select and load a stored script file. ? save script: launches the ?file save? dialog box, allowing the user to save a script file to storage. ? clear script: clears the current script editor work area to prepare for writing a new script. ? run script: begins execution of the currently loade d script. execution runs sequentially. ? step delay: entered as an integer number between 0 and 1000 millisecond s. double-click with the left mouse button over the text box to begin edi ting the value, then press the enter key. ? insert line separator: inserts a comment at the current cursor po sition that represents a separating line. used to organize long scripts. ? append programming: inserts all the commands re quired to program the otp memory into the script editor at the current cursor location. ? save log: launches the ?file save? dialog box, allowing users to save the script log to a file. ? clear log: clears the script log. ? commands : displays the pop-up window shown in figure 40 , with a graphical set of commands to add to the script.
KTPF0100UG , rev. 2.0 freescale semiconductor 41 graphical user interface description 10.4.1 loading and running a script to load a preexisting script file, press the ?load script? button. the ?file load? dialog box will appear, allowing you to navigate to the directory where your script file is loca ted. select the file you want and press the ?open? button. figure 36. loading a script file the script editor work area will now be filled with the file content, and the file name will appear next to the "file:" label and also as an entry in the script log.
KTPF0100UG , rev. 2.0 42 freescale semiconductor graphical user interface description next, change the script?s step delay to allow delay between each command. for instance, 50 ms are used in the ex ample shown in figure 37 . to make this change, double-click with the left mouse button while pointing to the ?step delay? text box. the text box background color will tu rn pink, indicating the valu e is being changed, but has not yet been updated. enter the desired delay value, and pr ess the enter key. notice that the text box background color returns to white, indicating that your updated value has been accepted. figure 37. script dialog box
KTPF0100UG , rev. 2.0 freescale semiconductor 43 graphical user interface description press the ?run script? bu tton to execute the script. as the script ex ecutes, each command will appear sequentially in the script log. comments are ignored. when the script has completed, an entry in the script log will be made as shown in figure 38 . figure 38. running the script
KTPF0100UG , rev. 2.0 44 freescale semiconductor graphical user interface description 10.4.2 writing a new script to write your own scripts, begin by creating a comme nt header using the ?insert line separator? button. figure 39. inserting line separators
KTPF0100UG , rev. 2.0 freescale semiconductor 45 graphical user interface description proceed by manually writing the desired commands or us e the ?command? button to display a graphical command selector in a new window, as shown in figure 40 . ?
KTPF0100UG , rev. 2.0 46 freescale semiconductor graphical user interface description 10.4.2.1 syntax and command set delimiters ? ':' - is used as a separator ? '/' - anything after a '/' will be ignored. ? white spaces will be truncated. table 8. command list (2) command description write_i2c:: sends to i 2 c register . (3) read_i2c: reads the value of and di splays it in the script log. (3) vpgm:on enables the 8.0 v otp programming supply. vpgm:off disables the 8.0 v otp programming supply. vpgm:up: increases the otp programming voltage (vpgm) in dac steps. vpgm:down: decreases the otp programming voltage (vpgm) in dac steps. v3v3:on enables the 3.3 v system supply. v3v3:off disables the 3.3 v system supply. pwron:high releases the pwron signal to a high-impedance state, allowing the pf0100 to start up. pwron:low asserts the pwron signal low, forcing the pf0100 to shutdown. pwron:toggle asserts the pwron signal low, and then releases it to a high-impedance state, generating a power on event on the pf0100. delay: adds delay between script commands. note that delays are cumulative with the script delay set on the editor. delay is set in ms. gpio1:high releases the gpio1 signal to a high-impedance state. gpio1:low asserts the gpio1 signal low. gpio1:toggle asserts the gpio1 signal low, and then releases it to a high-impedance state. gpio2:high releases the gpio2 signal to a high-impedance state. gpio2:low asserts the gpio2 signal low. gpio2:toggle asserts the gpio2 signal low, and then releases it to a high-impedance state. sw1x:mode: sets the mode of operation of the sw1x regulator. the valid operators are as follows: ?off ?pfm ?pwm ? aps sw1x:vout: sets the sw1x output voltage in no rmal operation. operating range from 0.300 v to 1.875 v in 0.025 v steps.
KTPF0100UG , rev. 2.0 freescale semiconductor 47 graphical user interface description sw1x:vstby: sets the sw1x output voltage to the standby mode. operating range from 0.300 v to 1.875 v in 0.025 v steps. sw1x:off: sets the sw1x output voltage to th e off mode. operating range from 0.300 v to 1.875 v in 0.025 v steps. sw1x:ilim: enables/disables the sw1x current limit. valid operators: ?on ?off swx:mode: sets the mode of operation of the swx regulator. following are valid operators: ?off ?pfm ?pwm ? aps swx:vout: sets the swx output voltage to normal operation. full operating range from 0.300 v to 3.300 v divided into two operating ranges (4) : ? low voltage range > 0.300 v to 1.875 v in 0.025 v steps. ? high voltage range > 0.800 v to 3.300 v in 0.050 v steps. swx:vstby: sets the swx output voltage to the standby mode. full operating range from 0.300 v to 3.300 v divided in two operating ranges (4) : ? low voltage range > 0.300 v to 1.875 v in 0.025 v steps. ? high voltage range > 0.800 v to 3.300 v in 0.050 v steps. swx:off: sets the swx output voltage to the off mode. full operating range from 0.300 v to 3.300 v divided into two operating ranges (4) : ? low voltage range > 0.300 v to 1.875 v in 0.025 v steps. ? high voltage range > 0.800 v to 3.300 v in 0.050 v steps. swx:ilim: enables/disables the swx current limit. valid operators: ?on ?off swbst:vout: set the output voltage of the swbst regulator. valid output voltage: ?5.000 ?5.050 ?5.100 ?5.150 swbst:on enables swbst regulator swbst:off disables swbst regulator. vgenx:on enables the vgenx supply. vgenx:off disables the vgenx supply. vgenx:vout: sets the output voltage for vgenx supply. ? vgen1/2 operating range: 0.800 v to 1.550 v with 50 mv steps. ? vgen3/4/5/6 operating range: 1.800 v to 3.3 v with 100 mv steps. vrefddr:on enables the vrefddr supply. table 8. command list (2) command description
KTPF0100UG , rev. 2.0 48 freescale semiconductor graphical user interface description vrefddr:off disables the vrefddr supply. vsnvs:on enables the vsnvs supply vsnvs:off disables the vsnvs supply. pwron:float releases the pwron signal to a high-impedance state, allowing the pf0100 to start up. (legacy for revision a scripts) log commands log:swx: shows the current value of the for the swx regulator. log operators: ? vout = output voltage in normal operation. ? stby = output voltage in standby mode. ? off = output voltage in off mode. ? mode = current switching mode set. ? otp_vout = default power up voltage set through otp. ? otp_sequence = default power up sequence of regulator. log:vgenx: shows the current value of the for the vgenx regulator. log operators: ? vout = output voltage. ? enable = supply is enabled/disabled. ? otp_vout = default power up voltage set through otp. ? otp_sequence = default power up sequence of regulator. log:vswbst: shows the current value of the for the vswbst regulator. log operators: ? vout = output voltage. ? enable = supply is enabled/disabled. ? otp_vout = default power up voltage set through otp. ? otp_sequence = default power up sequence of regulator. log:vrefddr: shows the current value of the for the vrefddr regulator. log operators: ? enable = supply is enabled/disabled. ? otp_sequence = default power up sequence of regulator. log:vsnvs: shows the current value of the for the vsnvs regulator. log operators: ? vout = output voltage. ? otp_vout = default power up voltage set through otp. log:otp_pu_config: shows the current value set as default by otp. ? seq_clk_speed = programmed power up sequencing speed. ? dvs_clk_speed = programmed dvs speed. ? pwron_mode = programmed pwron pin active level. ? pgood_enable = power good mode is on/off. table 8. command list (2) command description
KTPF0100UG , rev. 2.0 freescale semiconductor 49 graphical user interface description log:int: shows the status of the corresponding interrupt bit. interrupt operators are as follows: ? 110_degrees ? 120_degrees ? 125_degrees ? 130_degrees ? sw1a_overcurrent ? sw1c_overcurrent ? sw2_overcurrent ? sw3a_overcurrent ? sw3b_overcurrent ? sw4_overcurrent ? swbst_overcurrent ? vgen1_overcurrent ? vgen2_overcurrent ? vgen3_overcurrent ? vgen4_overcurrent ? vgen5_overcurrent ? vgen6_overcurrent 2. all characters (except for the "float" subc ommand) have to be entered in uppercase. 3. the register and data values should be entered as he xadecimal numbers, for example: 0x20 is entered as 20. 4. the output voltage operating range is set during otp programming and cannot be changed under normal pmic control. table 8. command list (2) command description
KTPF0100UG , rev. 2.0 50 freescale semiconductor graphical user interface description figure 41 shows a small sample script wh ich enables the vgen1 supply and reads the sw1ab mode register. run this script by pressing the ?run script? button. note that the result for the read_i2c:23 command shows up in the script log as 0x08. figure 41. sample script confirm that the script has run correc tly by checking the expected results in the gui registers for the respective supplies.
? ?
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KTPF0100UG , rev. 2.0 freescale semiconductor 53 graphical user interface description finally, save the script so that it can be used again. pres s the ?save script? bu tton, then the ?save file? dialog box will appear. enter the desired script file name, including the ?.txt? file ext ension, then press the ?save? button. figure 44. saving a script
KTPF0100UG , rev. 2.0 54 freescale semiconductor graphical user interface description 10.5 loading a configuration file a configuration file is a .txt file wh ich contains specific otp configuratio n instructions ready to be loaded and programmed into the otp memory, thereby setting up a defin itive power-up configuration for the pmic. to load a configuration script file, press the ?loa d configuration? button. an ?open file? dialog box will appear so that you can browse for and select your desired script file. once you have selected the file you want, press the ?open? button. script editor figure 45. loading a configuration file when the file has loaded, an entry in the log list will be made, and you should see the selected file displayed in the file i/o box.
c:\freescale\kitpf0100\_prf.txt KTPF0100UG , rev. 2.0 freescale semiconductor 55 graphical user interface description figure 46. scripting tab the ?save configuration? button can be used to extrac t the current values of the pf0100 otp extended page 1 registers from 0xa0 to 0xff and place them in a text file , creating a mirror image of the otp configuration of the pmic in use. remember to add the .txt file extension.
KTPF0100UG , rev. 2.0 56 freescale semiconductor graphical user interface description 10.6 programming an external pf0100 through j36 if the kitpf0100epevbe is used as an ex ternal programmer for either a customer bo ard or a dedicated pf0100 programming socket, j36 provides the re quired signals for such a task, howev er, it will be necessary to isolate the communication signals from the on-board pmic by doing the following: 1. verify that j22 is not in position 1-2 2. verify that j17 is not in position 1-2 3. verify that j30 is not in position 1-2 4. remove r43 (bottom layer) 5. remove r46 (bottom layer) 6. remove r47 (bottom layer) bh1 j34 j36 j35 j17 gnd1 bh2 r56 r60 c72 c74 c73 r66 q8 r77 r78 r43 q6 c66 c63 r74 c62 d8 d5 c57 j39 gnd4 j41 j40 c71 r55 c75 u4 r59 r63 r64 r65 r61 c76 c80 c59 u2 l10 d9 r48 r49 c64 c58 u5 r73 r47 c65 j5 c61 r41 y1 r46 c60 vin_swb1 lx_swb1 d7 j3 lx_swa1 vin_swa1 swab1 j30 ictest1 standby1 gnd6 resetbmcu1 j1 j27 j25 j31 q5 q10 q9 r76 r75 gnd3 r71 c79 vgen2 c81 c78 vin_swc1 vgen1 r72 d6 vin1 swc1 lx_swc1 vddotp1 j22 intb1 vin_sense1 sdwnb1 j33 j42 j10 j11 vin_sw4 sw4 lx_sw4 j6 vin_sw2 vin2 vcoredig1 vcoreref1 lx_swbst1 vin_swbst1 vswbst1 sda1 scl1 vddio1 r80 j44 j8 j12 j13 gnd2 sw2 lx_sw2 vrefddr1 vinrefddr1 j7 vin_swb3 lx_swb3 vcore1 vin3 pwron1 j9 c85 r81 r82 u7 r83 c86 j29 j15 vgen3 vgen4 vhalf1 swb3 swa3 j4 lx_swa3 vin_swa3 vgen6 vgen5 j20 j2 vsnvs1 j26 j24 j32 bh3 j14 j16 j18 j21 j19 j43 bat2 gnd5 bh4 s4 s3 s1 1 5 7 1 5 1 16 c + 1 s2 5 + a 1 2 3 1 a c ac 25 2 6 8 1 1 2 1 6 2 1 1 9 8 + 1 13 24 3 12 1 48 c a 4 3 2 1 1 1 1 1 19 20 3 1 3 1 2 2 1 + + 5 1 4 a c 1 1 1 1 2 1 1 1 1 1 2 1 1 1 1 4 1 3 5 1 20 19 1 1 1 1 1 1 1 1 1 1 1 1 1 19 1 2 - 2 20 + + 3 r47 r46 r43 f 47 itpf0100epevbe b v - c l a pf0 100 t otp b
KTPF0100UG , rev. 2.0 freescale semiconductor 57 graphical user interface description if you would like the kitpf0100gui to verify that a part has been programmed with the otp data supplied by the programming script, click the ?verify af ter programming? check box. this will direct the gui to do a line-by-line comparison between the data written and the data actually programmed into the part. ? ?
KTPF0100UG , rev. 2.0 58 freescale semiconductor graphical user interface description figure 49. scripting log session example note: if it is desired to carry o ut one-time programming of the pf0100 device soldered on the kitpf0100epevbe evaluation board, ensur e that the board hardware is correc tly configured according to the chosen otp settings. furthermore, the kitp f0100epe vbe allows the configur ation of the sw2 regulator or an external 3.3v ldo output as the vddio/i 2 c pull-up supply. by default, the sw2 regulator is the source for the vddio supply (j30 = 3-2). if the sw2 regulator is to be set below 3.0v then make sure the 3.3v ldo output is connected to vddio and the i 2 c pull-up resistors by removing r34 and r 33 and shorting pins 1, 2 and 3 of j30.
KTPF0100UG , rev. 2.0 freescale semiconductor 59 kitpf0100epevbe board layout 11 kitpf0100epevbe board layout 11.1 assembly layer top bh1 j34 d11 d10 j35 c77 j36 c37 c36 j17 gnd1 bh2 l9 r42 r45 f1 l11 r67 r68 r51 gnd4 vin_swb1 lx_swb1 r50 j39 r79 swab1 j41 c39 j40 j25 j5 c26 c25 r11 r10 r8 c23 j3 vin_swa1 c22 c21 r7 c24 j1 j30 lx_swa1 gnd6 j27 resetbmcu1 r37 r36 j31 vgen1 gnd3 vgen2 swc1 vin1 c82 lx_swc1 vin_swc1 r20 c6 r9 c10 r21 c3 r6 c9 l4 l3 c2 r30 r31 r85 c87 r35 r29 vddotp1 c1 l2 r32 r33 r34 r4 j22 ictest1 standby1 sdwnb1 intb1 d2 r84 vin_sense1 vddio1 r39 r38 q2 d3 q3 j33 lx_sw4 sw4 vin_sw4 j6 j10 j11 vin_sw2 c28 c29 c27 l5 r22 l6 c35 c11 c34 c49 c14 c48 c44 c41 c38 c13 c12 c19 c56 u1 c4 r2 c51 c20 r28 c55 c53 c17 c52 c54 r1 c83 vswbst1 r3 c16 c15 vcoreref1 scl1 d1 l1 r69 d4 j8 r40 sda1 q1 lx_sw2 sw2 gnd2 j13 j12 vin2 j7 c45 c40 c7 r26 r27 l8 c8 c84 r16 c32 r70 r24 c50 c46 c18 c47 c43 r23 r25 c42 c5 l7 vin_swbst1 lx_swbst1 pwron1 vcore1 vcoredig1 j9 j29 vgen3 j15 vgen4 vrefddr1 vhalf1 vinrefddr1 lx_swb3 vin_swb3 r17 swa3 swb3 j4 c33 vin_swa3 vgen6 vgen5 lx_swa3 vin3 c31 c30 vsnvs1 j20 j2 j32 j24 j26 bh3 j14 j16 j18 j19 j21 gnd5 sw1 bat1 bh4 1 1 1 3 4 6 13 4 2 j8 j12 j13 1 1 1 1 2 1 1 1 j29 j15 1 1 1 1 1 1 j32 j14 1 j16 1 1 j18 1 1 j19 1 1 2 j21 s4 s3 ac c a 5 1 7 1 5 1 s2 1 1 s1 1 5 2 6 8 1 1 2 1 6 2 1 1 1 1 1 1 j31 j25 1 1 2 1 2 1 1 c a c a 1 1 1 1 j33 j11 j10 1 1 2 14 15 29 28 1 1 43 42 56 1 2 c a f 50 a t l
KTPF0100UG , rev. 2.0 60 freescale semiconductor kitpf0100epevbe board layout 11.2 assembly layer bottom bh1 j34 j36 j35 j17 gnd1 bh2 r56 r60 c72 c74 c73 r66 q8 r77 r78 r43 q6 c66 c63 r74 c62 d8 d5 c57 j39 gnd4 j41 j40 c71 r55 c75 u4 r59 r63 r64 r65 r61 c76 c80 c59 u2 l10 d9 r48 r49 c64 c58 u5 r73 r47 c65 j5 c61 r41 y1 r46 c60 vin_swb1 lx_swb1 d7 j3 lx_swa1 vin_swa1 swab1 j30 ictest1 standby1 gnd6 resetbmcu1 j1 j27 j25 j31 q5 q10 q9 r76 r75 gnd3 r71 c79 vgen2 c81 c78 vin_swc1 vgen1 r72 d6 vin1 swc1 lx_swc1 vddotp1 j22 intb1 vin_sense1 sdwnb1 j33 j42 j10 j11 vin_sw4 sw4 lx_sw4 j6 vin_sw2 vin2 vcoredig1 vcoreref1 lx_swbst1 vin_swbst1 vswbst1 sda1 scl1 vddio1 r80 j44 j8 j12 j13 gnd2 sw2 lx_sw2 vrefddr1 vinrefddr1 j7 vin_swb3 lx_swb3 vcore1 vin3 pwron1 j9 c85 r81 r82 u7 r83 c86 j29 j15 vgen3 vgen4 vhalf1 swb3 swa3 j4 lx_swa3 vin_swa3 vgen6 vgen5 j20 j2 vsnvs1 j26 j24 j32 bh3 j14 j16 j18 j21 j19 j43 bat2 gnd5 bh4 s4 s3 s1 1 5 7 1 5 1 16 c + 1 s2 5 + a 1 2 3 1 a c ac 25 2 6 8 1 1 2 1 6 2 1 1 9 8 + 1 13 24 3 12 1 48 c a 4 3 2 1 1 1 1 1 19 20 3 1 3 1 2 2 1 + + 5 1 4 a c 1 1 1 1 2 1 1 1 1 1 2 1 1 1 1 4 1 3 5 1 20 19 1 1 1 1 1 1 1 1 1 1 1 1 1 19 1 2 - 2 20 + + 3 f 51 a l b
KTPF0100UG , rev. 2.0 freescale semiconductor 61 kitpf0100epevbe board layout 11.3 top layer routing figure 52. top layer routing
KTPF0100UG , rev. 2.0 62 freescale semiconductor kitpf0100epevbe board layout 11.4 inner layer 1 routing figure 53. inner layer 1 routing
KTPF0100UG , rev. 2.0 freescale semiconductor 63 kitpf0100epevbe board layout 11.5 inner layer 2 routing figure 54. inner layer 2 routing
KTPF0100UG , rev. 2.0 64 freescale semiconductor kitpf0100epevbe board layout 11.6 bottom layer routing 170-27458 rev b f 55 b l r
KTPF0100UG , rev. 2.0 freescale semiconductor 65 bill of materials 12 bill of materials item qty assy opt schematic label value/description part number manufacturer 1 1 bat1 battery lithium -- 3v 5.5mah ms621f-fl11e sii micro parts ltd. 2 1 bat2 holder coin cell 6.8mm smt bk-879 memory protection devices inc 3 4 bh1, bh2, bh3, bh4 mounting hole 0.130 inch, not a part to orderr not a part to order no mfg 4 7 c1, c3, c5, c8, c9, c12, c13 cap cer 4.7 f 10v 10% x5r 0603 5 7 c2, c6, c10, c11, c14, c44, c45 cap cer 0.1 f 10v 10% x5r 0402 6 5 c4, c7, c19, c56, c77 cap cer 0.1 f 10v 10% x7r 0402 7 1 c15 cap cer 0.01 f 50v 10% x7r 0402 8 14 c16, c21, c22, c25, c26, c27, c28, c29, c30, c31, c32, c33, c82, c83 cap cer 22 f 10v 20% x5r 0805 9 1 dnp c17 cap cer 1000pf 50v x7r 5% 0402 10 1 c18 cap cer 10 f 10v 10% x7r 0805 11 5 c20, c34, c38, c42, c43 cap cer 2.2 f 6.3v 20% x5r 0402 12 1 dnp c23 cap cer 22 f 10v 20% x5r 0805 13 1 dnp c24 cap cer 22 f 10v 10% x7r 1210 14 2 c35, c41 cap cer 4.7 f 6.3v 20% x5r 0402 15 3 c36, c37, c39 cap cer 10 f 16v 10% x7r 0805
KTPF0100UG , rev. 2.0 66 freescale semiconductor bill of materials 16 9 c40, c48, c49, c50, c51, c52, c54, c84, c87 cap cer 1.0 f 10v 10% x5r 0402 17 2 c46, c53 cap cer 0.22 f 16v 10% x7r 0402 18 1 c47 cap cer 0.47 f 10v 10% x7r 0402 19 1 dnp c55 cap cer 1.0 f 10v 10% x5r 0402 20 5 c57, c58, c62, c63, c65 cap cer 0.1 f 16v 10% x5r 0402 21 1 c59 cap tant 10 f 16v 10% -- 3216-18 22 3 c60, c61, c72 cap cer 22pf 25v 5% c0g 0402 23 1 c64 cap cer 0.47 f 16v 10% x7r 0603 24 1 c66 cap tant 4.7 f 10v 10% -- 3216-18 25 1 c71 cap tant esr 0.600 ohms 15 f 25v 10% -- 3528-21 26 1 c73 cap tant 4.7 f 25v 10% -- 3528-21 27 1 c74 cap cer 0.1 f 25v 10% x5r 0402 28 1 c75 cap cer 1.0 f 25v 10% x5r 0603 29 1 c76 cap cer 0.1 f 6.3v 10% x7r 0402 30 2 c78, c86 cap cer 470pf 50v 5% cog 0603 31 1 dnp c79 cap cer 2.2 f 16v 10% x5r 0603 32 1 c80 cap cer 1.0 f 16v 10% x5r 0603 33 1 c81 cap tant esr=1.800 ohms 2.2 f 10v 10% 3216-18 34 1 dnp c85 cap cer 2.2 f 6.3v 20% x5r 0402 item qty assy opt schematic label value/description part number manufacturer
KTPF0100UG , rev. 2.0 freescale semiconductor 67 bill of materials 35 1 d1 diode sch pwr rect 1a 20v smt mbr120lsft1g on semiconductor 36 3 d2, d3, d11 led red sgl 30ma 0603 sml-lxfm0603sic-tr lumex 37 1 d4 led dual grn/red 30ma smt ltst-c195kgjrkt lite on 38 4 d5, d6, d7, d8 diode tvs esd prot ult low cap 5-5.4v sod-923 esd9l5.0st5g on semiconductor 39 1 d9 diode sch pwr rect 1a 30v sod-123 mbr130lsft1g on semiconductor 40 1 d10 led grn sgl 30ma smt 0603 sml-lxfm0603sugctr lumex 41 1 f1 fuse plysw 0.5a 13.2v smt microsmd050f-2 raychem 42 56 dnp - test point red 40 mil drill 180 mil th 109l 43 13 j1, j2, j3, j4, j5, j6, j7, j9, j24, j26, j27, j40, j41 hdr 1x2 th 100mil sp 339h au 118l 44 9 j8, j10, j11, j12, j13, j14, j15, j31, j33 subassembly con 1x2 tb th 3.81mm sp 201h -- 138l + term block plug 3.81mm 2pos 45 7 j16, j18, j19, j21, j25, j29, j32 subassembly con 1x3 tb th 3.81mm sp 201h -- 138l + term block plug 3.81mm 3pos 46 2 j17, j35 hdr 2x3 th 100mil ctr 335h au 95l 47 4 j20, j22, j30, j39 hdr 1x3 th 100mil sp 340h au 118l 48 1 j34 con 5 usb mini-b ra shld skt smt 31mil sp au 675031340 molex 49 1 j36 hdr 2x4 th 100mil ctr 425h au 310l 50 3 dnp j42, j43, j44 hdr 2x10 smt 100mil sp 383h au 51 1 l1 ind pwr 2.2uh@100khz 2.0a 20% smt lps3015-222ml_ coilcraft 52 1 l2 ind pwr 1uh@100khz 6a 20% smt xal4020-102mec coilcraft item qty assy opt schematic label value/description part number manufacturer
KTPF0100UG , rev. 2.0 68 freescale semiconductor bill of materials 53 4 l3, l4, l5, l8 ind pwr 1uh@100khz 2.4a 30% smt lps4012-102nlc coilcraft 54 1 l6 ind pwr 1uh@1mhz 2a 30% smt vls252010t-1r0n tdk 55 1 l7 ind pwr 1uh@100khz 2.65a 20% smt lps5015-102mlc coilcraft 56 1 l9 ind fer 100 ohm@100mhz 8a 25% smd/1812 hi1812v101r-10 laird technologies 57 1 l10 ind pwr chk 22uh@1khz 1a 20% smd 744773122 wurth elektronik eisos gmbh & co. kg 58 1 l11 ind fer 100 ohm@100mhz 8a 25% smd/1812 hi1812v101r-10 laird technologies 59 1 q1 tran mosfet dual n & p channel 2.5v s-sot6 fdc6327c fairchild 60 2 q2, q3 tran pmos sw 120ma 25v sot23 fdv302p fairchild 61 3 q5, q6, q10 tran pmos sw 2a 30v ssot3 fdn360p fairchild 62 2 q8, q9 tran nmos 50v 220ma sot-23 bss138 fairchild 63 6 r1, r3, r4, r6, r8, r16 res -- 0.001 ohm 1/4w 5% 0805 lmi-r001-5.0 isabellenhtte heusler gmbh & co. kg 64 1 dnp r2 res mf 1.0 ohm 1/16w 1% 0402 65 5 dnp r7, r9, r10, r17, r70 res -- 0.001 ohm 1/4w 5% 0805 lmi-r001-5.0 isabellenhtte heusler gmbh & co. kg 66 1 r11 res mf 0.001 ohm 1w 1% 1206 csnl1206ft1l00 stackpole electronics 67 5 dnp r20, r23, r24, r27, r33 res mf zero ohm 1/10w 1% 0603 68 6 r21, r22, r25, r26, r34, r85 res mf zero ohm 1/10w 1% 0603 69 2 r28, r41 res mf 1.0m 1/16w 1% 0402 70 2 r29, r79 res mf 100k 1/16w 5% 0402 item qty assy opt schematic label value/description part number manufacturer
KTPF0100UG , rev. 2.0 freescale semiconductor 69 bill of materials 71 3 r30, r31, r32 res mf 10.0k 1/16w 1% 0402 72 6 r35, r43, r46, r47, r73, r74 res mf zero ohm 1/10w -- 0402 73 4 r36, r37, r50, r51 res mf 4.70k 1/16w 1% 0402 74 4 r38, r39, r40, r69 res mf 200 ohm 1/10w 1% 0402 75 2 r42, r45 res mf 33.0 ohm 1/16w 1% 0402 76 2 dnp r48, r49 res mf 1.5k 1/16w 5% 0402 77 1 r55 res mf 100 ohm 1/10w 1% 0603 78 1 r56 res mf 604k 1/16w 1% 0402 79 1 r59 res mf 374k 1/16w 1% 0402 80 2 r60, r76 res mf 470k 1/16w 1% 0402 81 1 r61 res mf 120k 1/16w 1% 0402 82 3 r63, r64, r65 res mf 10k 1/16w 5% 0402 83 2 r66, r75 res mf 47k 1/16w 1% 0402 84 2 r67, r68 res mf 470 ohm 1/16w 1% 0402 85 1 r71 res mf 20k 1/10w 5% 0603 86 1 r72 res mf 12.0k 1/10w 1% 0603 87 2 r77, r78 res mf 100k 1/16w 1% 0402 88 1 r80 res mf 27k 1/16w 5% 0402 89 1 r81 res mf 470k 1/16w 5% 0402 90 3 dnp r82, r83, r84 res mf zero ohm 1/10w -- 0402 91 1 dnp sw1 sw spst pb 12v 50ma smt item qty assy opt schematic label value/description part number manufacturer
KTPF0100UG , rev. 2.0 70 freescale semiconductor bill of materials 92 1 u1 ic power management consumer/industrial qfn56 mmpf0100npep freescale semiconductor 93 1 u2 ic mcu 8bit 48mhz 60kb flash 2.7-5.5v qfn48 mc9s08jm60cgte freescale semiconductor 94 1 u4 ic dac ctrl boost inv +/-27.5v -- 2.7-5.5v qsop16 max686eee+ maxim 95 2 u5, u7 ic lin vreg ldo 1.5-15v 150ma 2.5-16v sot23-5 mic5205ym5 micrel 96 1 y1 xtal 12mhz ser 9pf smt ecs-120-9-42x-ckm-tr ecs inc. international freescale does not assume liability, endorse, or warrant component s from external manufacturers that are referenced in circuit drawings or tables. while freescale offers component recommendatio ns in this configuration, it is the customer?s responsibility to validate their application item qty assy opt schematic label value/description part number manufacturer
document number description url mmpf0100 data sheet http://cache.freescale.com/files/analog/doc/data_sheet/mmpf0100.pdf mmpf0100er errata http://cache.freescale.com/files/analog/doc/errata/mmpf0100er.pdf pfseriesfs fact sheet http://cache.freescale.com/files/ analog/doc/fact_sheet/pfseriesfs.pdf an4622 layout application note http://cache.freescale.com/files/analog/doc/app_note/an4622.pdf product summary page www.freescale.com/mmpf0100 tool summary page www.freescale.com/kitpf0100epevbe analog home page www.freescale.com/analog power management home page www.freescale.com/pmic KTPF0100UG , rev. 2.0 freescale semiconductor 71 references 13 references 13.1 support visit freescale.com/support for a list of phone numbers within your region. 13.2 warranty visit freescale.com/warranty for a list of phone numbers within your region.
KTPF0100UG , rev. 2.0 72 freescale semiconductor revision history 14 revision history revision date description of changes 1.0 11/2012 ? initial release 2.0 2/2013 ? updated document for the latest gui revision 3.0.0.20 ? added figure 14. to section 8 evaluation board schematic ? added tbb operation mode. ? updated section 10.4 using the script editor ? updated section 10.5 loading a configuration file
KTPF0100UG , rev. 2.0 freescale semiconductor 73 revision history
document number: KTPF0100UG rev. 2.0 2/2013 information in this document is provided solely to enable system and software implementers to use freescale products. there are no express or implied copyright licenses granted hereunder to design or fa bricate any integrated circuits on the information in this document. freescale reserves the right to make chang es without further notice to any products herein. freescale makes no warranty, representation, or guarantee regarding the suitability of its products for any particul ar purpose, nor does freescale assume any liability arising out of the application or us e of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. ?typical? parameters that may be provided in freescale data sheets and/or specifications can and do vary in differ ent applications, and actual performance may vary over time. all operating parameters, including ?typicals,? must be validated for each customer application by customer?s te chnical experts. freescale does not convey any license under its patent rights nor the rights of others. freescale sells products pursuant to standard terms and conditions of sale, which can be found at the following address: http://www.reg.net/v2/webservices/freescale/docs/termsandconditions.htm freescale, the freescale logo, altivec, c-5, codetest, codewarrior, coldfire, c-ware, energy efficient solutions logo, mobilegt, powerquicc, qoriq, qorivva, starcore, and symphony are trademarks of freescale semiconductor, inc., reg. u.s. pat. & tm. off. airfast, beekit, beestack, coldfire+, co renet, flexis, magniv, mxc, platform in a package, processor expert, qoriq qonverge, quicc engine, ready play, smartmos, turbolink, vybrid, and xtrinsic are trademarks of freescale semiconductor, inc. all other product or service names are the property of their respective owners. ? 2013 freescale semiconductor, inc. how to reach us: home page: freescale.com web support: freescale.com/support

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